Last week, I had the honour of chairing a breakfast briefing hosted by OnX Enterprise Solutions, to discuss the results of a piece of research they recently did with a consortium of leading IT vendors, which looked at the performance of various FIX engines through a real-world, highly optimised technology stack.
The briefing was well-attended with 60+ people in the room (who can’t all have been there just for the free sausage & bacon rolls!).
David Quarrell of OnX – who I’m sure is already well known to regular HFT Review readers through his blog – kicked off procedings with an overview of how the consortium was put together, an explanation of what exactly was tested and a summary of the results.
The full report can be downloaded from the HFT Review website here, but in brief, some of the key findings of the research were:
- Commercial FIX engines are substantially faster, suffer from far less jitter and have much more deterministic latency than open source alternatives.
- The Java FIX engine on test performed just as well as the C++ engine.
- The Intel® Xeon® X5698 processor (4.4GHz) gave 36% better perfomance than the X5680 (3.33GHz)
- Use of kernel bypass further improved performance
Following on from David’s presentation, I chaired the panel session featuring Gordon Hughes of Intel, Paul Goodridge of Arista Networks and David Riddoch of SolarFlare Communications – all technology members of the consortium directly involved in building the test rig and integrating their components – and Kevin Houstoun of Rapid Addition, who provided one of the FIX engines under test (“Cheetah” in Java). Once each panelist had provided some background and context around their firm’s contribution to the research, we moved on to a more general discussion.
One of the topics we discussed was FPGAs. Even though FPGAs were not used in this particular piece of research, there was a lot of interest from both the panel and the audience on where they might be introduced into future tests, particularly for testing performance improvement on sequential events. The panel agreed that FPGAs may be challenging to work with in terms of the specialist knowledge required, but they will play an increasingly significant role in key aspects of high performance trading architectures.
Jitter was another topic of interest, as the panel discussed where it tends to occur (the software as opposed to the hardware layer) and what can be done to reduce it. Various ideas were discussed but a lot of it boiled down to efficient management of things like threading, memory allocation and garbage collection.
We also talked about PTP (Precision Time Protocol), which has been discussed in some depth on the HFT Review here, here, here and here. Again, PTP was not a part of this research but, as David Quarrell pointed out, if PTP had been used, it wouldn’t have made the results any more accurate but it certainly would have made the timing and clock synchronisation aspects of the tests much easier. So with future tests, PTP is likely to be included in the test rig.
All in all, it was an excellent session with some good interaction from the audience too.
Where do things go from here? OnX – and the other members of the consortium – are very keen to work with more technology vendors and ISVs to expand the scope of future tests. So if you work for a firm that supplies any kind of high performance trading technology (hardware or software), please feel free to get in touch with David Quarrell at OnX Enterprise Solutions, at [email protected]
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